According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad (paddle) is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features of outer leads is eliminated and no outer leads are necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants' own prior art LPCC process are discussed in Applicants' U.S. Pat. No. 6,229,200, issued May 8, 2001, the contents of which are incorporated herein by reference.
In another process, integrated circuit packages are gang fabricated by selectively plating up die attach pads and contact pads on a metal carrier strip. Singulated IC dice are then mounted on respective die attach pads using conventional die mount and epoxy techniques. After curing the epoxy, the dice are gold wire bonded to respective selectively plated contact pads. The packages are then molded in plastic or resin resulting in molded packages on a metal carrier strip. The carrier strip is then etched away and the individual packages are singulated by, for example, saw singulation. Again, the bottom of the die attach pad is exposed, thereby eliminating mold delamination problems at the bottom of the die attach pad and increasing moisture sensitivity performance. Again, the thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. All of the packages on the carrier strip are molded together by gang molding rather than molding individual pockets for each package. Clearly this increases manufacturing efficiency as compared to molding of individual packages.
The resulting package suffers from disadvantages, however. In particular, gang molding of the strip results in warping of the gang strip as a result of differences in the coefficients of thermal expansion in the carrier strip, the plastic or resin molding material and the integrated circuit dice. Also, each of the carrier strip, the molding material and the integrated circuit dice have different values of Young's Modulus and specific gravity. With these different material properties, warping of the molded strip results after molding.
For some packages, the use of a clear or transparent molding material is desirable. In such cases, no filler material is added to the molding material. The filler material is traditionally added to the molding material to change the coefficient of thermal expansion to more closely approach that of the Silicon material of the integrated circuit die. Without the filler, the mismatch in coefficient of thermal expansion between the mold compound, the integrated circuit die and the metal carrier is high, causing further warping. Also, the molding material shrinks after post mold curing due to cross linking of the resin in the mold compound. In extreme cases, warping of the strip prohibits singulation of individual packages. Due to warping problems, packages with clear or transparent mold material are not manufactured by gang fabrication on a metal carrier, as described above.
Further IC package improvements are still desirable and are driven by industry demands for increased thermal and electrical performance and decreased size and cost of manufacture.